The present invention relates to a dynamic random access memory device having a plurality of one transistor type memory cells each including one transfer gate transistor and one storage capacitor connected to the transfer gate transistor.
Recently, the surface area occupied by each memory cell has become smaller because of the increasing
number of memory cells on one semiconductor chip. Consequently, a sufficient capacitance of the storage capacitor is hardly obtained. To cope with this problem, a trench capacitor technology was proposed by, for example, Ralph J. Jaccodine et al. in U.S. Pat. No. 4,353,086, in which a trench is grooved from a major flat surface of a semiconductor substrate thereinto and a dielectric film of the capacitor is provided on the side wall of the trench. A capacitor electrode is formed on the dielectric film within the trench. In the prior art, the dielectric film is required to be a uniform thickness on all side wall portions including the lower portion adjacent to the bottom of the trench and the upper portion adjacent to the major surface of the substrate. In the prior art trench capacitor memory cell, however, an unfavorable leakage current is likely to flow between the capacitor electrode and the transistor in a level higher than that of a conventional planar capacitor type memory cell in which the storage capacitor is formed on the major flat surface of the substrate. The leakage current in the trench capacitor memory cell would be mainly flowed through the dielectric film between the capacitor electrode and the upper side wall portion of the trench formed by an impurity region having a conductivity type opposite to the raw substrate and connected to one of source and drain regions of the transistors. Therefore, the trench capacitor memory device in the prior art cannot be expected to generate a high production yield and a highly reliable device. Further, a thinner dielectric film for obtaining a higher capacitance cannot be realized in the prior art trench capacitor technology.